Array substrate for display device and method of manufacturing the same

ABSTRACT

An array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line, a semiconductor layer formed on the gate insulation layer, a contact hole formed through the passivation layer and the gate insulation layer to expose the data line and a source electrode and a drain electrode formed on the semiconductor layer. The capacitor electrode is overlapped with the data line. The source electrode is connected to the data line through the contact hole and the source electrode and the drain electrode include a transparent conductive material.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a divisional of U.S. patent application Ser.No. 12/178,967, filed on Jul. 24, 2008, which claims priority under 35U.S.C. §119 to Korean Patent Application No. 10-2008-0036727, filed onApr. 21, 2008, the disclosures of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present disclosure relates to an array substrate for a displaydevice and method of manufacturing a display device, and moreparticularly, to an array substrate capable of enhancing an apertureratio.

2. Discussion of the Related Art

A liquid crystal display (LCD) device which is one of the flat paneldisplay devices includes an array substrate, a countering substratefacing the array substrate and a liquid crystal layer interposed betweenthe array substrate and the countering substrate. The LCD device isprovided with a pixel electrode and a common electrode to apply anelectric field to each liquid crystal cell. The pixel electrode isformed on the array substrate, whereas the common electrode is formed onthe countering substrate. Each of the pixel electrodes is connected to adrain electrode of a thin film transistor (TFT). The pixel electrodealong with the common electrode drives the liquid crystal cell byapplying an electric filed in response to a data signal applied via theTFT.

Since an arrangement of liquid crystals in the liquid crystal layer canbe adjusted by an electric field, a light transmittance of the liquidcrystal layer is changed, thereby displaying an image.

In order to improve a brightness of the LCD device, an aperture ratio ofthe LCD device is required to be increased. However, the aperture ratiois reduced since a distance between the pixel electrode and a data lineis maintained to avoid the parasitic capacitance generated by a couplingeffect therebetween, and since a wide black matrix is required to covera possible misalignment of the two substrates.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide a method ofmanufacturing a display substrate capable of enhancing an aperture ratioand an array substrate for a display device using the same.

According to an exemplary embodiment of the present invention, an arraysubstrate includes a substrate, a data line formed on the substrate, apassivation layer formed on the data line, a gate line including a gateelectrode and a capacitor line formed on the passivation layer, a gateinsulation layer formed on the gate electrode and the capacitor line, asemiconductor layer formed on the gate insulation layer, a contact holeformed through the passivation layer and the gate insulation layer toexpose the data line, and a source electrode and a drain electrodeformed on the semiconductor layer. The capacitor electrode is overlappedwith the data line. The source electrode is connected to the data linethrough the contact hole and the source electrode and the drainelectrode comprises a transparent conductive material.

The drain electrode comprises a pixel electrode formed on the gateinsulation layer.

The pixel electrode comprises one of a reflective conductive material, atransflective conductive material, indium tin oxide (ITO) and indiumzinc oxide (IZO).

A width of the capacitor line is wider than a width of the data line.

According to an exemplary embodiment of the present invention, a displaydevice includes a first substrate, a second substrate including a blackmatrix and a liquid crystal layer interposed between the first substrateand the second substrate. The first substrate includes a data lineformed on the substrate, a passivation layer formed on the data line, agate line including a gate electrode and a capacitor line that is formedon the passivation layer and is overlapped with the data line, a gateinsulation layer formed on the gate electrode and the capacitor line, asemiconductor layer formed on the gate insulation layer, a contact holeformed through the passivation layer and the gate insulation layer toexpose the data line, and a source electrode and a drain electrodeformed on the semiconductor layer. The drain electrode includes a pixelelectrode formed on the gate insulation layer, and a width of adjacentpixel electrodes being narrower than a width of the black matrix, awidth of the capacitor line and a width of the data line.

The source electrode and the drain electrode include a transparentconductive material.

The transparent conductive material includes one of a reflectiveconductive material, a transflective conductive material, indium tinoxide (ITO) and indium zinc oxide (IZO).

A width of the capacitor line is wider than a width of the data line.

According to an exemplary embodiment of the present invention, a methodof manufacturing an array substrate includes forming a data line on asubstrate, forming a passivation layer on the data line, forming a gateline including a gate electrode and a capacitor line on the passivationlayer, forming a gate insulation layer on the gate electrode and thecapacitor line, forming a semiconductor layer on the gate insulationlayer, forming a contact hole through the passivation layer and the gateinsulation layer to expose the data line, and a source electrode and adrain electrode on the semiconductor layer. The capacitor electrode isoverlapped with the data line. The source electrode is connected to thedata line through the contact hole and the source electrode and thedrain electrode include a transparent conductive material.

The method of manufacturing an array substrate further includes formingan ohmic contact layer between the semiconductor layer and the sourceelectrode and the drain electrode.

The transparent conductive material comprises one of a reflectiveconductive material, a transflective conductive material, indium tinoxide (ITO) and indium zinc oxide (IZO).

A width of the capacitor line is wider than a width of the data line.

According to an exemplary embodiment of the present invention, a methodof manufacturing a display device includes forming a first substrate,forming a second substrate including a black matrix, and forming aliquid crystal layer between the first substrate and the secondsubstrate.

Forming the first substrate includes forming a data line on thesubstrate, forming a passivation layer on the data line, forming a gateline including a gate electrode and a capacitor line that is formed onthe passivation layer and is overlapped with the data line, forming agate insulation layer on the gate electrode and the capacitor line,forming a semiconductor layer on the gate insulation layer, forming acontact hole through the passivation layer and the gate insulation layerto expose the data line, and forming a source electrode and a drainelectrode on the semiconductor layer.

The drain electrode includes a pixel electrode formed on the gateinsulation layer, and a width of adjacent pixel electrodes beingnarrower than a width of the black matrix, a width of the capacitor lineand a width of the data line.

The method of the display device further includes forming an ohmiccontact layer between the semiconductor layer and the source electrodeand the drain electrode.

The pixel electrode includes one of a reflective conductive material, atransflective conductive material, indium tin oxide (ITO) and indiumzinc oxide (IZO).

A width of the capacitor line is wider than a width of the data line.The capacitor line entirely covers the data line.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the present invention can be understood in moredetail from the following descriptions taken in conjunction with theaccompanying drawings, in which:

FIG. 1 is a plan view of an array substrate according to an exemplaryembodiment of the present invention;

FIG. 2 is a cross-sectional view taken along a line A-A′ of FIG. 1;

FIG. 3 is a plan view of an array substrate according to an exemplaryembodiment of the present invention;

FIG. 4 is a cross-sectional view taken along a line B-B′ of FIG. 3;

FIG. 5 is a plan view of an array substrate according to an exemplaryembodiment of the present invention;

FIG. 6 is a cross-sectional view taken along a line C-C′ of FIG. 5;

FIG. 7 is a plan view of an array substrate according to an exemplaryembodiment of the present invention;

FIG. 8 is a cross-sectional view taken along a line D-D′ of FIG. 7;

FIG. 9 is a plan view of an array substrate according to an exemplaryembodiment of the present invention;

FIG. 10 is a cross-sectional view taken along a line E-E′ of FIG. 9;

FIG. 11 is an enlarged plan view showing a portion X of FIG. 9; and

FIG. 12 is a cross-sectional view taken along a line F-F′ of FIG. 11.

DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

The invention is described more fully hereinafter with reference to theaccompanying drawings, in which exemplary embodiments of the inventionare shown. This invention may, however, be embodied in many differentforms and should not be construed as limited to the exemplaryembodiments set forth herein.

FIG. 1 is a plan view of an array substrate according to an exemplaryembodiment of the present invention. FIG. 2 is a cross-sectional viewtaken along a line A-A′ of FIG. 1.

Referring to FIGS. 1 to 2, an array substrate 10 includes a substrate100, a data line 110 formed on the substrate 100 and a passivation layer120 formed on the data line 110.

The substrate 100 may include, for example, transparent glass to passthrough light. The glass may have a non-alkaline characteristic. Thesubstrate 100 may include transparent synthetic resin such as, forexample, triacetylcellulose TAC, polycarbonate PC, polyethersulfone PES,polyethyleneterephthalate PET, polyethylenenaphthalate PEN,polyvinylalcohol PVA, polymethylmethacrylate PMMA and cyclo-olefinpolymer COP. The data line 110 may include, for example, a conductivematerial. The conductive material having a low resistivity may include,for example, an aluminum-based material, a copper-base material, asilver-base material, a molybdenum-based material, and a titanium-basematerial. The data line 110 may include, for example, a single-layeredstructure as well as a multiple-layered structure. The multiple-layeredstructure may include a first layer having a low resistivity and a goodcontacting property. The data line 110 may further include a data pad(not shown). The passivation layer 120 may include an insulation layer,for example, an organic insulation layer, silicon nitride, or anacrylic-based material.

FIG. 3 is a plan view of an array substrate according to an exemplaryembodiment of the present invention. FIG. 4 is a cross-sectional viewtaken along a line B-B′ of FIG. 3.

Referring to FIGS. 3 to 4, a gate line 130 including a gate electrode140 and a capacitor line 150 are formed on the passivation layer 120. Agate insulation layer 160 is formed on the gate line 130 and thecapacitor line 150.

The gate lines 130 are extended substantially parallel with each other.

The gate line 130 may include, for example, metal or a conductivematerial such as aluminum (Al), aluminum alloy, molybdenum (Mo),molybdenum alloy, chromium (Cr), chromium alloy, tantalum (Ta), tantalumalloy, copper (Cu) or copper alloy. The gate line 130 may include, forexample, a single-layered structure as well as a multiple-layeredstructure. The multiple-layered structure may include a first layerhaving a low resistivity and a good contacting property. The gate line130 may further include a gate pad.

In an exemplary embodiment, the gate electrode 140 is not overlappedwith the data line 110.

The capacitor line 150 is overlapped with the data line 110. In anexemplary embodiment, a width of the capacitor line 150 is wider than awidth of the data line 110 so that the capacitor line 150 entirelycovers the data line 110. The capacitor line 150 may be formed by a samematerial of the gate line 130.

The gate insulation layer 160 may include an insulation layer, forexample, an organic insulation layer, a silicon nitride layer (SiNx), asilicon oxide layer (SiOx), or an acrylic-based material. In anexemplary embodiment, the gate insulation layer 160 may include amultiple-layered structure. The multiple-layered structure may include,for example, a first gate insulation layer (not shown) having a firstdielectric property and a second gate insulation layer (not shown)having a second dielectric property.

FIG. 5 is a plan view of an array substrate according to an exemplaryembodiment of the present invention. FIG. 6 is a cross-sectional viewtaken along a line C-C′ of FIG. 5.

Referring to FIGS. 5 and 6, a semiconductor layer 170 that functions asan active layer is formed on the gate insulation layer 160. Thesemiconductor layer 170 is formed in an island shape on the gateinsulation layer 160. The semiconductor layer 170 may include, forexample, amorphous silicon or polycrystalline silicon. In addition, thesemiconductor layer 170 may include a mixed oxide, such as ZnO, InZnO,InGaO, InSnO, ZnSnO, GaSnO, GaZnO, or GaInZnO. The mixed oxide for thesemiconductor layer 170 has good ohmic contact characteristics to thesource electrode 210 and the drain electrode 220, such that an ohmiccontact layer is not needed.

An ohmic contact layer (not shown) may be formed on the semiconductorlayer 170. The ohmic contact layer is divided with respect to the gateelectrode 140. The ohmic contact layer may include, for example,silicide of metal, N+ amorphous silicon or doped microcrystallizedamorphous silicon.

FIG. 7 is a plan view of an array substrate according to an exemplaryembodiment of the present invention. FIG. 8 is a cross-sectional viewtaken along a line D-D′ of FIG. 7.

Referring to FIGS. 7 and 8, a first contact hole 180 is formed throughthe passivation layer 120 and the gate insulation layer 160 to exposethe data line 120. A second contact hole (not shown) and a third contacthole (not shown) may be formed through the passivation layer 120 and thegate insulation layer 160 to expose the gate pad and the data pad.

FIG. 9 is a plan view of an array substrate according to an exemplaryembodiment of the present invention. FIG. 10 is a cross-sectional viewtaken along a line E-E′ of FIG. 9. FIG. 11 is an enlarged plan viewshowing a portion X of FIG. 9. FIG. 12 is a cross-sectional view takenalong a line F-F′ of FIG. 11.

Referring to FIGS. 9 through 12, a source electrode 210 and a drainelectrode 220 are formed on the semiconductor layer 170 and the gateinsulation layer 160. The source electrode 210 and the drain electrode220 may include a transparent conductive material.

The source electrode 210 is electrically connected to the data line 110through the first contact hole 180.

The drain electrode 220 may include a pixel electrode 230 formed on thegate insulation layer 160. The pixel electrode 230 may include, forexample, a reflective conductive layer, a transflective conductivelayer, indium tin oxide (ITO) or indium zinc oxide (IZO).

Referring to FIG. 10, a countering substrate 20 includes a black matrix310. A liquid crystal layer 320 is disposed between the array substrate10 and the countering substrate 20.

The black matrix 310 can block light leakage.

In an exemplary embodiment, a distance d of adjacent pixel electrodes231, 232 is narrower than a width of the black matrix 310, a width ofthe capacitor line 150 and a width of the data line 110.

In one embodiment of the invention, a conductive layer (not shown) isformed on a substrate 100. A photo resist layer (not shown) is formed onthe conductive layer. The photo resist layer is patterned to form aphotolithography mask (not shown). Then, the conductive layer ispatterned through the photolithography mask to form a data line 110 asillustrated in FIG. 2.

An insulation layer is coated on the substrate 100 having the data line110 to form a passivation layer 120 as illustrated in FIG. 2.

A conductive layer (not shown) is formed on the passivation layer 120,and a photo resist layer (not shown) is formed on the conductive layer.The photo resist layer is patterned to form a photolithography mask (notshown). Then, the conductive layer is patterned through thephotolithography mask to form a gate line 130 including a gate electrode140 and a capacitor line 150 as illustrated in FIG. 4. In an embodimentof the invention, the capacitor line 150 may be overlapped with the dataline 110.

An insulation layer is coated on the substrate 100 having the data line110 to form a gate insulation layer 160 as illustrated in FIG. 4.

A semiconductor material layer (not shown) is formed on the gateinsulation layer 160. The semiconductor material layer is patterned by aphotolithography process to form a semiconductor layer 170 asillustrated in FIG. 6. In an embodiment of the invention, an ohmiccontact layer may be formed on the semiconductor layer 170.

A photo resist layer (not shown) is coated on the semiconductor layer170 and the gate insulation layer 160. The photo resist layercorresponding to the data line 110 is removed. The gate insulation layer160 and the passivation layer 120 corresponding to the data line 110 arepatterned by a full exposure process so that the data line 110 isexposed. Thus, a contact hole 180 is formed as illustrated in FIG. 8.

A transparent conductive layer (not shown) is formed on thesemiconductor layer 170 and the gate insulation layer 160. A photoresist layer is coated on the transparent conductive layer. The photoresist layer is patterned to form a photolithography mask (not shown).Then, the transparent conductive layer is patterned through thephotolithography mask to form a source electrode 210 and a drainelectrode 220. The source electrode 210 is electrically connected to thedata line 110 through the contact hole 180. The drain electrode 220includes a pixel electrode 230 as illustrated in FIG. 12.

A black matrix 310 is formed on a countering substrate 20. A liquidcrystal layer 320 is interposed between the array substrate 10 and thecountering substrate 20 as illustrated in FIG. 10.

In an embodiment of the invention, a distance (d) of adjacent pixelelectrodes (231, 232) is narrower than a width of the black matrix, awidth of the capacitor line and a width of the data line.

According to exemplary embodiments, a display device including the arraysubstrate and the countering substrate can enhance an aperture ratio

Although the illustrative embodiments of the present invention have beendescribed herein with reference to the accompanying drawings, it is tobe understood that the present invention should not be limited to thoseprecise embodiments and that various other changes and modifications maybe affected therein by one of ordinary skill in the related art withoutdeparting from the scope or spirit of the invention. All such changesand modifications are intended to be included within the scope of theinvention as defined by the appended claims.

1. A method of manufacturing an array substrate, the method comprising:forming a data line on a substrate; forming a passivation layer on thedata line; forming a gate line including a gate electrode and acapacitor line on the passivation layer, wherein the capacitor electrodeis overlapped with the data line; forming a gate insulation layer on thegate line and the capacitor line; forming a semiconductor layer on thegate insulation layer; forming a contact hole through the passivationlayer and the gate insulation layer to expose the data line; and forminga source electrode and a drain electrode on the semiconductor layer,wherein the source electrode is connected to the data line through thecontact hole, and the source electrode and the drain electrode comprisesa transparent conductive material.
 2. The method of claim 1, furthercomprising: forming an ohmic contact layer between the semiconductorlayer and the source electrode and the drain electrode.
 3. The method ofclaim 1, wherein the transparent conductive material comprises one of atransflective conductive material, indium tin oxide (ITO) and indiumzinc oxide (IZO).
 4. The method of claim 1, wherein a width of thecapacitor line is wider than a width of the data line.
 5. The method ofclaim 1, wherein the semiconductor layer is formed on an island shape onthe gate insulation layer.
 6. The method of claim 1, wherein thesemiconductor layer comprises at least one of amorphous silicon andpolycrystalline silicon.
 7. The method of claim 1, wherein thesemiconductor layer comprises a mixed oxide at least one of ZnO, InZO,InGaO, InSnO, ZnSnO, GaSnO, GaZnO, and GaInZnO.
 8. A method ofmanufacturing a display device, the method comprising: forming a firstsubstrate, wherein forming the first substrate comprises: forming a dataline on the substrate; forming a passivation layer on the data line;forming a gate line including a gate electrode and a capacitor line thatis formed on the passivation layer and is overlapped with the data line;forming a gate insulation layer on the gate line and the capacitor line;forming a semiconductor layer on the gate insulation layer; forming acontact hole through the passivation layer and the gate insulation layerto expose the data line; and forming a source electrode and a drainelectrode on the semiconductor layer, forming a second substrateincluding a black matrix; and forming a liquid crystal layer between thefirst substrate and the second substrate, wherein the drain electrodecomprises a pixel electrode formed on the gate insulation layer, and adistance of adjacent pixel electrodes is narrower than a width of theblack matrix, a width of the capacitor line and a width of the dataline.
 9. The method of claim 8, further comprising: forming an ohmiccontact layer between the semiconductor layer and the source electrodeand the drain electrode.
 10. The method of claim 8, wherein the pixelelectrode comprises one of a reflective conductive material, atransflective conductive material, indium tin oxide (ITO) and indiumzinc oxide (IZO).
 11. The method of claim 8, wherein a width of thecapacitor line is wider than a width of the data line.
 12. The method ofclaim 11, wherein the capacitor line entirely covers the data line. 13.The method of claim 8, wherein the semiconductor layer is formed on anisland shape on the gate insulation layer.
 14. The method of claim 8,wherein the semiconductor layer comprises at least one of amorphoussilicon and polycrystalline silicon.
 15. The method of claim 8, whereinthe semiconductor layer comprises a mixed oxide at least one of ZnO,InZO, InGaO, InSnO, ZnSnO, GaSnO, GaZnO, and GaInZnO.